Synthesizable VHDL and Verilog HDL IP Cores.

Digital Core Design (DCD) complete IP solutions provider and SoC design house offers VHDL and Verilog synthesizable IP cores supported by DoCD TM Debug System for 8 and 16-/32-bit processors, floating point IEEE-754 units, I2C, SPI, MAC, UARTs and other speed, size and power consumption optimized cores.